In a process of developing semiconductor integrated circuits such as a large scale integrated circuit (LSI), almost always, a design method using a computer aided design (CAD) tool is employed. Such a design environment using a CAD tool is also refereed to as an electronic design automation (EDA) environment. In such a semiconductor development process incorporating the CAD tool, desired semiconductor circuits are created in an LSI with the use of a hardware description language such as VHDL and Verilog. Also in this process, functions of the semiconductor circuits thus designed are evaluated through a software simulator called a device logic simulator.
A device logic simulator includes an interface commonly called a testbench through which test data (vector) is applied to the design data showing the intended semiconductor circuits, thereby evaluating the response of the intended semiconductor circuits resulted from the test data.
After the design stage of the LSI circuit, actual LSI devices are produced and are tested by a semiconductor test system, such as an LSI tester, to determine whether the LSI devices properly perform the intended functions. An LSI tester supplies a test pattern (test vector) to an LSI device under test and compares the resultant outputs of the LSI device with expected data to determine pass/fail of the LSI device. For testing an LSI device with higher levels of functionality and density, a test pattern to be applied to the LSI device must accordingly be complex and lengthy, resulting in significantly large work load and work hours in producing the test patterns. Therefore, it is not preferable to produce the test patterns when an LSI device under test is actually produced, especially as to LSI devices of shorter life cycles, because it causes a time delay to put the LSI devices into market.
Thus, to improve an overall test efficiency and productivity of the semiconductor integrated circuits, it is a common practice to apply the data produced through the operation of the device logic simulator in the design stage of the integrated circuits to an actual test of the semiconductor integrated circuits. In general, a test procedure performed by an LSI tester in testing a semiconductor integrated circuit has a substantial similarity to the test procedure by the device logic simulator in the CAD process noted above for testing the design data of the semiconductor circuit. For example, test patterns and expected value patterns for an LSI tester to test the intended semiconductor integrated circuits are produced by utilizing the resultant data (dump file) produced by executing the device logic simulation. However, as of today, there is no system which is able to produce test patterns and expected data patterns to be used in an LSI tester and to evaluate the same, with high speed and low cost but without information errors, based on the dump file derived from the logic simulation of the LSI devices.
In such logic simulation data, test patterns to be applied to a device model as well as the resultant outputs (expected value patterns) of the device model are expressed by an event base. Here, the event base data expresses the points of change (events) in a test pattern from logic "1" to logic "0" or vice versa with reference to the passage of time. Generally, such time passage is expressed by a time length from a predetermined reference point or a time length from a previous event. In contrast, in an actual LSI tester, test patterns are described by a cycle base. In the cycle base data, test patterns are defined relative to predetermined test cycles (tester rates) of the tester.
As in the foregoing, test patterns for testing LSI devices actually produced are efficiently created by using the CAD data produced in the design stage of the LSI devices. However, because of various reasons, test patterns produced for an LSI tester in this manner may not always be appropriate to accurately detect failures of the LSI device under test. Thus, it is necessary to evaluate the test patterns produced through the foregoing procedure.
In the conventional technology, in evaluating the test patterns to be used in an LSI tester created with the use of the logic simulation data, there are basically two methods, one that uses an actual LSI tester and the other that does not use an LSI tester. In the method of using an actual LSI tester, it is necessary to extract event base test patterns in the logic simulation data and convert the same to cycle base test patterns. Such test patterns in the cycle base is run in the actual LSI tester to evaluate the correctness of the test patterns. This method is disadvantageous in that an expensive LSI tester is used only for evaluating an integrity of the test patterns.
In the method of not using an LSI tester, an LSI tester simulator is used for evaluating the test patterns. In this method as well, the LSI tester simulator debugs the test patterns that have been converted to the cycle base. For simulating the functions of the LSI device under test which receives the test pattern from the LSI tester simulator, a logic simulator is used which is created during the design process using the CAD tool. Since all of the evaluation process is performed through software processes, this method is disadvantageous in that it requires a very long time to finish the evaluation.
An example of the conventional technology without using the actual LSI tester is described in more detail below. FIG. 1 is an example of conventional technology for evaluating test patterns with the use of a tester simulator and a logic simulator, i.e., an example in which all of the operations are performed by software.
In FIG. 1, an LSI simulator 11 formed of software is provided with pattern data and timing data created for an LSI tester from a pattern file 10.sub.1 and a timing file 10.sub.2. The pattern data and the timing data are created, for example, by extracting pattern data and timing data from a dump file 15 resulted in performing a logic simulation in the design stage of the LSI device. An example of the logic simulator dump file is VCD (Value Change Dump) of Verilog. The data in the dump file 15 is converted to cycle base data by a conversion software 17, resulting in the pattern data and timing data noted above stored in the pattern file 10.sub.1 and the timing file 10.sub.2, respectively.
The LSI tester simulator 11 is to debug the test patterns to test the intended LSI device or the function of the LSI device without using an LSI tester hardware. The LSI tester simulator 11 generates a test pattern having pattern information and timing information and applies the test pattern to the logic simulator of the LSI device to be tested. The LSI tester simulator 11 compares the resultant output signals from the logic simulator with the expected data to determine the correctness of the test pattern or performances of the intended LSI device.
The LSI tester simulator 11 provides the test pattern to a format converter 12 as input data. The format converter 12 converts the input data from the LSI tester simulator 11 to a format to be accepted by a device logic simulator 13. Generally, the device logic simulator 13 includes an interface called PLI (Programming Language Interface). Thus, in such a case, the format converter 12 converts the test pattern to the PLI format.
The device logic simulator 13 is the simulator that has been used in the design stage of the LSI device and is formed of a logic simulator 13.sub.1 and a device model 13.sub.2 described in a language which is able to communicate with the logic simulator 13.sub.1. The device model 13.sub.2 simulates the operation of the LSI device to be tested. The device logic simulator 13 sends the test pattern received through the PLI interface to the device model 13.sub.2 and provides the resultant response from the device model 13.sub.2 to a format converter 14 through the PLI interface. The format converter 14 converts the output of the device model 13.sub.2 to a format to be received by the LSI tester simulator 11. The LSI tester simulator 11 compares the device output data from the format converter 14 with the expected value data. When both data mach, it is considered that the test pattern is correct.
In evaluating the test pattern solely by the software process using the device logic simulator as in the foregoing, it requires a large amount of work and a very long processing time. The time required for operating the device logic simulator accounts for the most part of the overall processing time.